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Design of flash memory arrays with SOI cells utilizing the back-channel based erase method

B. LONČAR1,* , P. OSMOKROVIĆ2, Z. STANOJEVIĆ2, M. VUJISIĆ2

Affiliation

  1. Faculty of Technology and Metallurgy, University of Belgrade, Karnegijeva 4, 11120 Belgrade, Serbia
  2. Faculty of Electrical Engineering, University of Belgrade, Bulevar Kralja Aleksandra 73, 11120 Belgrade, Serbia

Abstract

This paper demonstrates one way of designing a flash memory array which incorporates cells produced in Silicon-On- Insulator (SOI) technology. General principles of SOI flash memory cell operation are presented. SOI memory cells used in the design utilize a standard way to write information and a novel method to erase it. Performance analysis of the suggested design is carried out for a simple memory array. 16x16 memory chip layout is presented as an example..

Keywords

Flash memory, SOI, Memory array, Design.

Submitted at: Aug. 12, 2007
Accepted at: Nov. 16, 2007

Citation

B. LONČAR, P. OSMOKROVIĆ, Z. STANOJEVIĆ, M. VUJISIĆ, Design of flash memory arrays with SOI cells utilizing the back-channel based erase method, Journal of Optoelectronics and Advanced Materials Vol. 9, Iss. 11, pp. 3576-3578 (2007)