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B. LONČAR1,* , P. OSMOKROVIĆ2, Z. STANOJEVIĆ2, M. VUJISIĆ2
Affiliation
- Faculty of Technology and Metallurgy, University of Belgrade, Karnegijeva 4, 11120 Belgrade, Serbia
- Faculty of Electrical Engineering, University of Belgrade,Bulevar Kralja Aleksandra 73, 11120 Belgrade, Serbia
Abstract
A quantitative analysis for describing and discussing design characterization of a SOI (Silicon-on-Insulator) flash memory cell is presented. Expressions for the front gate threshold voltage of a SOI memory cell are derived using equations for the standard SOI MOSFET. Coupling coefficients connecting the control gate with the source and drain region, and with the silicon bulk via charge stored at the floating gate, have to be included in these equations. In this way, the front gate voltage of the standard SOI MOSFET is equal to the voltage of the memory cell floating gate. During analysis, emphasis is put on the case when the back channel is depleted, because in that case coupling between the front and back gate can control the threshold voltage of the control gate. The derived expressions show the influence of the back voltage VG2 and device parameters on the threshold voltage of either the control or floating gate, when the device is fully depleted..
Keywords
SOI MOSFET, Threshold voltage, Coupling coefficients, Silicon film thickness.
Submitted at: Nov. 14, 2006
Accepted at: June 15, 2007
Citation
B. LONČAR, P. OSMOKROVIĆ, Z. STANOJEVIĆ, M. VUJISIĆ, Quantitative analysis of SOI memory cells, Journal of Optoelectronics and Advanced Materials Vol. 9, Iss. 6, pp. 1856-1860 (2007)
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